The invention relates to a circuit arrangement for adjusting the bit rates of two signals of which the signal having the higher bit rate is structured in frames, wherein the circuit arrangement comprises a buffer memory, a write counter and a read counter as well as a phase comparator and a control circuit for inserting positive or negative stuff bits between the bits of the lower bit rate signal.
Circuit arrangements for bit rate adjustment in information transmission systems are necessary, for example, in plesiochronous multiplexers which multiplex plesiochronous signals. Two binary signals are termed plesiochronous when their bit rates are nominally the same, but may in fact deviate from a nominal value within a given tolerance. Before plesiochronous signals can be multiplexed by a plesiochronous multiplexer, they all have to be brought to the same (10% higher) bit rate, for example, by means of a circuit arrangement having the features described above. The ratio of the input bit rate to the frame frequency denotes the number of bits of the lower bit rate signal which are to be inserted in a frame. If this ratio for the nominal value of the two magnitudes is an integer, two techniques can be distinguished: First the positive-zero-negative stuffing technique and secondly the positive-negative stuffing technique.
If in the first case the instantaneous clock frequency of the lower bit rate signal is equal to the nominal bit rate, all bits of this signal which arrive each second can be inserted in the frames of the higher bit rate signal, without the need for inserting positive or negative stuff bits (variable stuff bits are denoted here).
If in the second case the instantaneous clock frequency of the lower bit rate signal is equal to its nominal value, positive and negative stuff bits are inserted alternately.
A positive stuff bit refers to a bit without information content at a location usually carrying an information or data bit, whereas a negative stuff bit transmits a data bit to a location otherwise occupied by a fixed stuff bit. The fixed stuff bits are used for the coarse frequency adjustment and may contain additional and secondary information for the receiver.
In an article--to be referenced (1) in the following--by Grover et al. (Grover, W. D.; Moore, T. E.; McEachern, J. E.: Measured Pulse Stuffing Jitter in Asynchronous DS-1/Sonet Multiplexing with and without Stuff-Threshold Modulation Circuit, Electronics Letters (1987), Vol. 23, pp. 959 to 961), a circuit arrangement is described with which the above operations of stuff bit insertion can be performed. An arrangement of this type comprises an addressable buffer memory, in which a first signal is written by means of a write counter and from which a second signal is read out by means of a read counter. If the circuit is located at the transmitter end, the first signal is written into the buffer memory with a bit clock and the write counter is incremented with this clock. A control circuit drives the read counter with a clock in whose otherwise regular edge pattern certain edges are lacking. The pattern of the lacking edges reflects the frame structure. A phase comparator forms the difference between the write and read addresses, of which the magnitude is monitored and if a threshold is transgressed or fallen short of a signal is applied to the control circuit as a sign that a positive or negative stuff bit is to be inserted into the frame (stuff request). The control circuit then inserts with the write clock an additional edge at a specific location of the frame or removes an edge from the sample used thus far.
At the receiver end of the transmission system after a plesiochronous demultiplexer a corresponding circuit arrangement can be switched for removing again the positive and negative stuff bits and for bringing the bit rate back to its original value. The removal of the stuff bits is again effected via a buffer memory in which the useful data are written. The reading operation controls a phase-locked loop for producing a clock frequency which is as uniform as possible (presents little jitter). By jitter is meant the deviation of the clock edges from their nominal value. Strict requirements are made on jitter suppression in accordance with CCITT Recommendation G. 823. High-frequency spectral portions in the jitter can be reduced at the receiver end by the low-pass phenomenon of the phase control loop. However, a randomly low-frequency spectral portion of the so-called stuff jitter (cf. the article by D. L. Duttweiler: Waiting Time jitter; Bell System Technical Journal 51, (1972), pp. 165 to 207) may develop, whose amplitude can be controlled or reduced respectively, only when stuffing is performed (thus at the transmitter end).
In order to reduce this jitter it is proposed in the article by Grover et al. to use sawtooth modulation for the threshold of the threshold detector.